1. Field of the Invention
The present invention relates to a semiconductor device having a mushroom- or T-shaped gate electrode, and to a method of fabricating the mushroom or T-shaped gate electrode. More specifically, the present invention relates to a semiconductor device having a gate electrode whose upper surface is relatively large so as to accommodate a metal silicide, and to a method of fabricating a gate electrode wherein the upper surface of the gate electrode is enlarged.
2. Description of the Related Art
Recent sub-micron integrated circuit technology aims at continuously reducing the line width and contact area of the semiconductor device, whereby the length of the gate lines of integrated circuits is continuously decreasing. In general, shortening the gate line increases the electrical resistance of the gate line (hereinafter, referred to as line resistance), resulting in a corresponding reduction in the operating speed of the gate line. That is, the operating speed in an integrated circuit is mainly dependent on a delay time, and the line resistance and parasitic capacitance between the gate lines have a decisive effect on the delay time. Accordingly, increases in the operating speed of the integrated circuit must be achieved by reducing the line resistance or reducing the parasitic capacitance by widening the space between the gate lines.
Most of the technology has focused on decreasing the line resistance to improve the operating speed of the integrated circuit because the alternative solution of widening the space between the gate lines runs counter to the aim of achieving a high degree of integration of the integrated circuit. A recent technological trend involves the use of a polycide layer to minimize the line resistance. Specifically, a suicide layer including a metal having a high melting point is coated on an upper portion of a gate electrode formed of polysilicon, and the silicide layer is incorporated with the gate electrode by a heat treatment to form the polycide layer.
However, when the line width of the integrated circuit is less than 0.13 μm, the length and width of the gate electrode are correspondingly small, and the surface area of the gate electrode is also extremely small. Accordingly, the contact area between the gate electrode and the metal used to form the silicide layer is so small that the silicide layer is not sufficiently incorporated into the gate electrode by the heat treatment. That is, when the line width is less than 0.13 μm, the resistance of the polycide layer on the gate electrode is unstable and hence, the polycide layer does not reduce the electrical resistance at the gate electrode.
Delay time also results from the parasitic capacitance generated in a region of overlap between the gate electrode and the substrate. In the fabricating of semiconductor devices, the gate electrode is first formed of polysilicon on the substrate such that a dimension of the gate electrode conforms to the length of a channel layer under the gate electrode, and then source/drain electrodes are subsequently formed through an ion implantation process. A plurality of dopants are injected into an active region of the substrate to form the source/drain electrodes, and a heat treatment is performed for stabilizing the substrate. However, the dopants diffuse to the edge portion of the gate electrode due to the heat. Accordingly, the source and drain electrodes extend to locations beneath the gate electrode at both edge portions thereof. Accordingly, the channel layer is shortened by an amount corresponding to the amount of overlap between the gate electrode and the source/drain electrodes (short channel effect). The overlapping portion acts as a parasitic capacitor between the gate electrode and the substrate because the overlapping portion is electrically non-conductive. When an electrical current is applied to the source electrode, the parasitic capacitor is first charged and then, the current passes into the drain electrode through the channel layer. Therefore, a time delay is produced according to the time it takes to charge the parasitic capacitor. That is, the parasitic capacitance (hereinafter referred to as “overlay parasitic capacitance”) reduces the operating speed of the integrated circuit. The operating speed is also reduced due to an overlay parasitic capacitor created as the result of a halo ion implantation process for preventing the diffusion of the source/drain dopants.
Ways to improve the resistance characteristic of the polycide gate electrode have been researched in connection with the fabricating of semiconductor devices having a design rule of less than 0.1 μm. For example, U.S. Pat. No. 6,169,017 (issued to Tong-Hsin Lee) discloses a technique of enlarging the upper surface of the gate electrode with which the silicide layer is to contact, whereupon the gate electrode is T-shaped or mushroom-shaped. Furthermore, Japanese Laid-Open Patent Publication No. 2000-36594 discloses a method of fabricating a polycide gate electrode, wherein polysilicon is twice deposited on a substrate such that an upper portion of the gate electrode is larger than the lower portion thereof. However, these techniques each fail to prevent the occurrence of a time delay due to the overlay parasitic capacitance between the gate electrode and substrate.